Intel EM64T - Extended
Memory 64 Technology
32-bit operating systems
have a limitation of 4GB of memory address space. This
limitation is put upon every device or application
running in the system that initiates IOs into system
memory, such as graphics cards and Ethernet
controllers. Each device shares a piece of that 4GB of
available memory space in 32-bit mode. However, a 64-bit
architecture will expand addressable memory space from
4GB to a possible 256 terabytes, which obviously allows
for an exponentially larger shared memory space for
system IOs.
Where 32-bit
workstations and servers are currently typically offered
with 4GB of system RAM, many OEMs will be offering 16GB
and higher Intel Pentium 4 and Xeon configurations
moving forward. Incidentally Intel's Xeon processor
lineup has had EM64T support for some time and even
older Prescott core CPUs have had this feature, although
Intel hadn't enabled it until this processor launch.
EM64T is nearly
completely compatible with AMD64 technology and is
simply an
extension of the 32-bit x86 or IA-32 instruction
set. Although Intel will not openly acknowledge this, it
is a very close facsimile to what AMD has offered for
some time in the Athlon 64 and is very different from
Intel's own IA-64 instruction set that Intel brought to
market with the Itanium. As a result, EM64T-capable
processors cannot run the same software, OS, or
applications developed for IA-64. With the success of
the Athlon 64, especially in the workstation/server
markets, Intel simply had to respond to this competitive
threat. Although it's a bitter pill to swallow, Goliath
bowed to David in this battle, and Intel followed a
competitor's path in X86 CPU technology, something the
company hasn't had to do for a very long time.
Intel Enhanced
SpeedStep Power Savings and Thermal Control
EIST or Enhanced Intel
SpeedStep Technology, is an Intel innovation that Intel
has been developing in its mobile Pentium processor
designs for some time now. It's a method of allowing the
system to dynamically adjust processor frequency as well
as voltage. Requirements to support EIST are dynamic VID
support on the motherboard, based on the VRD10 power
array specification, BIOS EIST support, OS Support for
EIST, and System Configuration to enable EIST. Virtually
all motherboard manufacturers offering i915 and 9125X
designs will have built-in BIOS EIST
support. Furthermore, here is a current list of
operating systems that support EIST:
• Microsoft Windows XP
SP2
• Microsoft Advanced Server 2003 SP1 (builds > 1218)
• General Linux 2.6.9 kernel and beyond
What actually happens
in the case of a Pentium 660, for example, is that at
very light workloads or an idle state, the processor
kicks down to a 14X multiplier for 2.8GHz and core
voltage is brought down in scale. During medium or heavy
workloads, the processor returns to full specification
speed in the case of a P4 660, which is 3.6GHz. We'll
show this in action later in this article. This
technology was absolutely pivotal for Intel to realize
more reasonable thermal characteristics because these
new Prescott 2M cores, with their additional L2 cache on
board, drive core temperatures to nearly alarming
levels.
Execute Disable Bit
For Security
Certain viruses that
compromise a system can create buffer overflows by
swamping a system processor with code. This overflow can
potentially allow the worm or virus to propagate itself
across a network of systems infecting other computers in
the network. Execute Disable Bit technology was
developed by Intel initially for its Itanium processor
line, aimed at preventing these types of buffer overflow
attacks. Now also available in these new Pentium 4
processors, the Execute Disable Bit allows the processor
to designate areas in system memory where application
code can run and areas where it can't. When a virus or
worm tries to compromise the memory buffer, the system
processor stops the code execution, halting the worm or
virus in its tracks.
2MB of L2 Cache
Intel has recently
taken another path to enhancing processor performance
beyond just brute force clock speed increases. Larger
on-chip cache regions allow for significantly lower
latency memory access in support of the P4 Prescott 2M
core. Sufficient memory bandwidth is a significant
system bottleneck in general, and the Prescott 2M core,
with its 31-stage pipe, needs all the bandwidth it can
get. 2MB of L2 cache should provide a measurable
performance gain over current Prescott core P4 CPUs and
afford this processor core a bit more headroom in gaming
and multimedia applications. Comparatively, the Prescott
2M core that these new 6XX Sequence and 3.73GHz Extreme
Edition CPUs are based on have 512KB less processor
cache on board than a Gallatin core Extreme Edition 3.4
or 3.46GHz P4, which also has a much shorter 20-stage
pipeline. Current P4 EE chips have 512KB L2 cache and
another full 2MB of L3 cache. It should be interesting
to see how these two new architectures match up and how
well the new Extreme Edition P4 fares against its
brethren Gallatin P4 EE chip.